Conference Papers
[15] Qiaochu Zhang*, Shiyu Su*, Zerui Liu*, Hsiang-Chun Cheng, Zhengyi Qiu, Mayank Palaria, Jiacheng Ye, Deming Meng, Buyun Chen, Sushmit Hossain, Wei Wu, and Mike Shuo-Wei Chen, “A Stochastic Analog SAT Solver in 65nm CMOS Achieving 6.6μs Average Solution Time with 100% Solvability for Hard 3-SAT Problems,” in IEEE VLSI Symposium on Technology and Circuits (VLSI), Jun. 2024 (* equal contribution)
[14] Qiaochu Zhang*, Shiyu Su*, Baishakhi Rani Biswas, Sandeep Gupta, and Mike Shuo-Wei Chen, “Synthesizable 10-bit Stochastic TDC Using Common-Mode Time Dithering and Passive Approximate Adder With 0.012mm² Active Area in 12nm FinFET,” in IEEE VLSI Symposium on Technology and Circuits (VLSI), Jun. 2024 (* equal contribution)
[13] Mayank Palaria, Shiyu Su, Hsiang-Chun Cheng, Rezwan A. Rasul, Qiaochu Zhang, Soumya Mahapatra, Chong Fatt Law, Sushmit Hossain, Ryan Bena, Wei Wu, Quan Nguyen, and Mike Shuo-Wei Chen, “Analog Kalman Filter with Integration and Digitization via a Shared Thyristor-Based VCO for Sensor Fusion in 65 nm CMOS,” in IEEE European Solid-State Circuits Conference (ESSCIRC), Sep. 2023.
[12] Shiyu Su*, Qiaochu Zhang*, and Mike Shuo-Wei Chen, “A 2GS/s 8.5-Bit Time-Based ADC Using a Segmented Stochastic Flash TDC,” in 2023 IEEE Custom Integrated Circuits Conference (CICC), Apr. 2023 (* equal contribution)
[11] Hsiang-Chun Cheng, Shiyu Su, Mayank Palaria, Qiaochu Zhang, Ce Yang, Sushmit Hossain, Ryan Bena, Buyun Chen, Zerui Liu, Juzheng Liu, Rezwan Rasul, Quan Nguyen, Wei Wu, Mike Shuo-Wei Chen, “A Memristor-Based Analog Accelerator for Solving Quadratic Programming Problems,” in 2023 IEEE Custom Integrated Circuits Conference (CICC), Apr. 2023
[10] Qiaochu Zhang, Hsiang-Chun Cheng, Shiyu Su, and Mike Shuo-Wei Chen, “A Fractional-N Digital MDLL with Injection Error Scrambling and Background Third-Order DTC Delay Equalizer Achieving –67dBc Fractional Spur,” in IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2023
[9] Qiaochu Zhang*, Shiyu Su*, and Mike Shuo-Wei Chen, “A Cost-Efficient Fully Synthesizable Stochastic Time-to-Digital Converter Design Based on Integral Nonlinearity Scrambling,” in 2022 59th IEEE/ACM Design Automation Conference (DAC), Jul. 2022 (* equal contribution)
[8] Shiyu Su, Qiaochu Zhang, Juzheng Liu, Mohsen Hassanpourghadi, Rezwan Rasul, and Mike Shuo-Wei Chen, “TAFA: Design Automation of Analog Mixed-Signal FIR Filters Using Time Approximation Architecture,” in IEEE/ACM 27th Asia and South Pacific Design Automation Conference (ASP-DAC), Jan. 2022
[7] Shiyu Su, Qiaochu Zhang, Mohsen Hassanpourghadi, Juzheng Liu, Rezwan Rasul, and Mike Shuo-Wei Chen, “Analog/Mixed-Signal Circuit Synthesis Enabled by the Advancements of Circuit Architectures and Machine Learning Algorithms,” in IEEE/ACM 27th Asia and South Pacific Design Automation Conference (ASP-DAC), Jan. 2022
[6] Mohsen Hassanpourghadi, Shiyu Su, Rezwan Rasul, Juzheng Liu, Qiaochu Zhang, and Mike Shuo-Wei Chen, “Circuit Connectivity Inspired Neural Network for Analog Mixed-Signal Functional Modeling,” in 2021 58th IEEE/ACM Design Automation Conference (DAC), Dec. 2021
[5] Qiaochu Zhang, Shiyu Su, Cheng-Ru Ho, and Mike Shuo-Wei Chen, “A Fractional-N Digital MDLL with Background Two-Point DTC Calibration Achieving -60dBc Fractional Spur,” in IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2021
[4] Juzheng Liu, Shiyu Su, Meghna Madhusudan, Mohsen Hassanpourghadi, Samuel Saunders, Qiaochu Zhang, Rezwan Rasul, Yaguang Li, Jiang Hu, Arvind Kumar Sharma, Sachin S. Sapatnekar, Ramesh Harjani, Anthony Levi, Sandeep Gupta, and Mike Shuo-Wei Chen, “From Specification to Silicon: Towards Analog/Mixed-Signal Design Automation using Surrogate NN Models with Transfer Learning,” in IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Nov. 2021
[3] Juzheng Liu, Mohsen Hassanpourghadi, Qiaochu Zhang, Shiyu Su, and Mike Shuo-Wei Chen, “Transfer Learning with Bayesian Optimization-Aided Sampling for Efficient AMS Circuit Modeling,” in IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Nov. 2020
[2] Qiaochu Zhang, Shiyu Su, Juzheng Liu, and Mike Shuo-Wei Chen, “CEPA: CNN-based Early Performance Assertion Scheme for Analog and Mixed-Signal Circuit Simulation,” in IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Nov. 2020
[1] Mohsen Hassanpourghadi, Qiaochu Zhang, Praveen Sharma, Jaewon Nam, Shiyu Su, Subhajit Chowdhury, Jagannathan Sathyamoorthy, Walter Unglaub, Fangzhou Wang, Mike Shuo-Wei Chen, Sandeep Gupta, Anthony Levi, Wes Hansford, and William Taylor, “Automated Analog Mixed Signal IP Generator for CMOS Technologies,” in Government Microcircuit Applications and Critical Technology Conference (GOMACTECH), 2019.
Journal Papers
[4] Qiaochu Zhang, Hsiang-Chun Cheng, Shiyu Su, and Mike Shuo-Wei Chen, “Fractional-N Digital MDLL with Injection-Error Scrambling and Calibration,” IEEE Journal of Solid-State Circuits, Jan. 2024
[3] Qiaochu Zhang, Shiyu Su, Cheng-Ru Ho, and Mike Shuo-Wei Chen, “A Fractional-N Digital MDLL with Background Two-Point DTC Calibration,” IEEE Journal of Solid-State Circuits, Jan. 2022
[2] Wu Zan, Qiaochu Zhang, Hu Xu, Fuyou Liao, Jing Wan, Jianan Deng, Hao Zhu, Lin Chen, Qingqing Sun, Shijin Ding, Peng Zhou, Wenzhong Bao, and David Wei Zhang, “Large Capacitance and Fast Polarization Response of Thin Polymer Electrolyte Dielectrics by Spin-Coating for Two Dimensional MoS2 Devices,” Nano Research, Dec. 2017
[1] Xiongfei Song, Zhongxun Guo, Qiaochu Zhang, Peng Zhou, Wenzhong Bao, and David Wei Zhang, “Progress of Large-Scale Synthesis and Electronic Device Application of Two-Dimensional Transition Metal Dichalcogenides,” Small, Jul. 2017